1. Field of the Invention
The present invention relates to pipelined analog to digital converters. Particularly, this invention discloses a new pipelined stage design which has a different scheme for producing the digital outputs and the analog residue.
2. Description of the Related Art
In the field of analog to digital (A/D) conversion, increasing the speed and precision of the conversions is desirable. For example, 5 MHz sampling rates are needed in hand-held CCD document scanners; high-end scanners and low-end video applications require 10 MHz sampling rates; and standardbroadcast video cameorders need 20 MHz sampling. Furthermore, high-end video applications take advantage of over-sampling at 25 MHz; automotive collision-avoidance radar receivers undersample at 25MHz, and medical ultrasound scanners and professional broadcast-studio video equipment want 40 MHz sampling rates. In addition, digital communication applications undersample in the 20-to-25 MHz range.
Today A/D converters need to produce as much as 40 Megasamples per second (MS/sec) at 12 bits per sample while still providing a reasonably low latency. There are several techniques currently used to achieve the speeds. For example, parallel-encoded flash, multi-step, pipeline, and time-interleaved successive approximation are some of the techniques.
Flash A/D encoding is the fastest method of conversion, because it is essentially performed in a single step. FIG. 1 shows a typical flash A/D structure. For an N-bit encoded output, the input voltage is sent to 2.sup.N comparators which each compare the input to a different reference voltage. All of the comparators whose reference voltage is higher than the input voltage will produce a logical true output. A priority encoder then generates a digital output corresponding to the lowest comparator whose output was activated. The delay time from input to output equals the sum of comparator plus encoder delays. Although this latency does not increase significantly with the size of the encoded output, the sheer size of the circuit essentially doubles with each additional output bit desired. Thus, the size of flash A/D makes that approach prohibitively expensive for many modern applications.
Multi-step encoding is a variant on the simple parallel flash encoding. A three-step twelve bit A/D is shown in FIG. 2. In the first stage, the four most significant bits are generated by a standard four bit flash circuit similar to the one discussed above. A four-bit digital to analog (D/A) converter then converts the output of the first stage back to analog. The difference in voltage between the input and the output of the converter is then fed into a second stage. The second stage has a reference voltage which is 2.sup.-4 times (one sixteenth) the reference voltage used in the first stage. The second most significant four bits are produced by the second stage, and another four bit D/A converts the value back into an analog signal, which is subtracted from the difference obtained from the subtractor of the previous stage. Finally, the last stage has a reference voltage which is 2.sup.-4 times the voltage of the previous stage, or 2.sup.-8 (one two-hundred-fifty-sixth) times the original reference voltage. This stage produces the four least significant bits of the result. All twelve bits are then latched, and the output is available for use.
Successive approximation is a prior art method of producing the output bits in order of descending significance. FIG. 3 is an example of a successive approximation circuit. In one implementation, all bits of the register are initially set to zero, then the most significant bit is set to a one, thus forming an initial guess. This guess is converted to analog by a D/A, and the output of the D/A is compared to the input voltage using a standard comparator. If the input voltage is higher than the analog guess, the most significant bit remains a one, otherwise, the most significant bit is set to back to zero. In the next steps, the next most significant bits are provisionally set to one, and comparisons are similarly done to determine each bit. Essentially, an iterative binary search is performed until the least significant bit is determined.
There are several other types of popular A/D converters which use charge balancing on a capacitor to facilitate A/D conversion. Some of those methods including voltage to frequency conversion, single-slope integration, dual-slope integration, delta-sigma converters, and switched capacitor converters. See, for example, Horowitz, P., and Hill, W., The Art of Electronics, 2nd Ed., Cambridge University Press, 1989, pp. 621-629.
Several of the above-mentioned A/D converter strategies can be pipelined. A typical N-bit pipelined A/D converter consists of J, K-bit stages, where J*K=N. For example, five stages (J=5) each producing 2 bits K=2) would result in a 10 bit converter.
FIG. 4A shows a single stage of a pipelined A/D converter. FIG. 4B shows a multistage pipeline architecture using the single stage of FIG. 4A. In FIG. 4A, the analog input is sampled and held. The result is converted to a K-bit digital code by a analog to digital subconverter. If this is the first stage, the K-bits produced are the most significant bits of the final output. This digital code is used by a local digital to analog converter to create the analog equivalent of the K-bit digital code. This estimate is then subtracted from the original analog input to create a residue, which is essentially the analog remainder. The resulting analog residue is then multiplied by 2.sup.K and sent to the next stage. The resulting residue can be calculated from the following formula. EQU Vres.sub.i =2.sup.K *(Vres.sub.i-1 -Vdac.sub.i) (1)
Each stage can be identically designed, unlike the multistage flash encoding discussed earlier, in which each successive stage has a lower reference voltage. In the pipelined A/D converter, because the residues are multiplied by 2.sup.K, each successive stage has the same range of input voltages, rather than having that range geometrically decreasing toward zero.
If the D/A converter in each stage is linear, the D/A converter output will be represented as follows. EQU Vdac.sub.l =D.sub.i *2.sup.-K *Vref (2)
In Equation 2, D.sub.i is the binary representation of the K-bit digital code determined in each stage. D.sub.i *2.sup.-K merely represent the fraction of V.sub.ref which has already been encoded and is to be subtracted from the analog remainder Vres.sub.i-1. V.sub.ref is set such that the input voltage Vres.sub.i will always be less than V.sub.ref. The remainder is multiplied by 2.sup.K before being sent to the next stage. The central problem with this scheme, however, is that the overall linearity of the total converter is dependent upon all the digital to analog conversions being linear. For a digital to analog conversion to be linear, the differences in output voltage Vdac.sub.i for each one bit increment of the input D.sub.i must all be equal.
There are two ways in which this problem has been attacked. The first way involves setting K=1. Thus, each stage produces only one bit. In this case, the analog to digital subconverter produces only a one bit code. If K=1, the digital to analog converter in each stage only has two possible output voltages. This D/A conversion will always be linear, since there is always a straight line that can be drawn between two points. In this case, the ideal gain of each converter stage is two. By substituting K=1, Equations 1 and 2 produce the following residue equation. EQU Vres.sub.i =2*Vres.sub.i-1 -D.sub.i *Vref (3)
It is helpful to think of D.sub.i as representing either of the two values -1 or +1. A simple circuit such as the one shown in FIG. 5 is typically used to generate the residue. Operation of this circuit is simple. A two-phase non-overlapping clock is used to generate control of the circuit.
FIG. 5A shows the circuit in its sampling phase. During the sampling phase, switches S.sub.1A, S.sub.1B, and S.sub.1C are all closed, and switches S.sub.2A and S2.sub.B are open. Switch S.sub.1C holds the operational amplifier as a follower. Switches S.sub.1A and S.sub.1B cause the input voltage Vres.sub.i-1 to be sampled on both capacitors Cap1 and Cap2, respectively. Thus, both capacitors are charged to a voltage of Vres.sub.i-1. A one-bit analog to digital converter is just a comparator. At this time, the comparator compares Vresi.sub.i-1 with ground, producing the digital output D.sub.i as follows. EQU D.sub.i =1 if Vres.sub.i -1&gt;0, and EQU D.sub.i =-1 if Vres.sub.i -1&lt;0 (4)
FIG. 5B shows the circuit in its output phase. During the second phase of the non-overlapping clock, switches S.sub.2A and S.sub.2B are closed, while switches S.sub.1A, S.sub.1B, and S.sub.1C are open. Capacitor Cap1 is connected to the output of the operational amplifier by Switch S.sub.2B, while Cap2 is connected by Switch S.sub.2A to either +V.sub.ref or -V.sub.ref depending on the digital output code D.sub.i. Assuming that Cap1 and Cap2 have equal capacitances C, by connecting Capacitor Cap2 to either +V.sub.ref or -V.sub.ref, the output of the operational amplifier is forced to the desired residue given by Equation 3.
However, in the non-ideal real world it is impossible to exactly realize the transfer function of Equation 3. First, it is impossible to make the capacitances of Cap1 and Cap2 exactly the same. The variable .alpha..sub.i represents the capacitor mismatch for stage i. Cap1 has a capacitance of C, while Cap2 has a capacitance of (1+.alpha..sub.i)*C. Second, a real operational amplifier does not have infinite gain and does not settle instantaneously, but rather has a finite gain and non-zero settling time. Errors due to the finite gain and non-zero settling time in stage i are represented by .epsilon..sub.i. Another source of error is charge injection onto the capacitors due to Switch S.sub.1C. Furthermore, an ideal operational amplifier has a zero output when the inputs are shorted together; in contrast, an actual operational amplifier has a non-zero output voltage when the inputs are shorted together due to imperfect matching of components within the operational amplifier. Vofs.sub.i represents the total offset in stage i due to the sum of charge injection effects and operational amplifier offset. When the three error factors .alpha..sub.i, .epsilon..sub.i, and Vofs.sub.i are introduced into the derivation, the real world transfer function is as follows. EQU Vres.sub.i =[(2+.alpha..sub.i)*Vres.sub.i -1-(1+.alpha..sub.i)D.sub.i *Vref](1-.epsilon..sub.i)+Vofs.sub.i ( 5)
FIG. 6A shows the ideal one bit per stage residue transfer function. The x-axis shows the range of input residues while the y-axis shows the resulting output residues. Note that the slope from (-V.sub.ref,-V.sub.ref) to (0,+V.sub.ref) and from (0,-V.sub.ref) to (+V.sub.ref,+V.sub.ref) is two; therefore, this stage has an ideal gain of two.
FIG. 6B shows the effect of capacitor mismatch .epsilon..sub.i. Capacitor mismatch errors do not shift the endpoints of the transfer characteristic, but they shift the slope and thus the residue at the transition points. If .alpha..sub.i is negative, Cap2 is less than Cap1, the slope of the transfer function is less than two, and the Vres.sub.i output range is less than -V.sub.ref to +V.sub.ref. On the other hand, if .epsilon..sub.i is positive, Cap2 is greater than Cap1, the slope of the transfer function is greater than two, and the Vres.sub.i output range is greater than -V.sub.ref to +V.sub.ref.
FIG. 6C shows the effect of errors due to finite operational amplifier gain and/or incomplete operational amplifier settling (.epsilon..sub.i). Error due to .epsilon..sub.i shifts the endpoints as well as introducing errors in the residue transfer characteristic at the transition points, while preserving the correct output only at the points (-V.sub.ref,0) and (+V.sub.ref,0).
FIG. 6D shows the effect of errors due to charge injection and operational amplifier offset (Vofs.sub.i). These errors shift the whole characteristic vertically. This does not introduce a gain error but the end points and the residue transfer characteristic at the transition point is shifted.
FIG. 6E shows the effect of errors due to comparator offset. These errors essentially just change input voltage Vres.sub.i-1 at which the transition from D.sub.i =-1 to D.sub.i =1 occurs. Instead of occurring at Vres.sub.i-1 =0, this transition will occur at some higher or lower input voltage. This does not introduce a gain error, but the end points and the residue transfer characteristic at the transition point is shifted. Errors due to comparator offset alter the Equations 4 governing the determination of the Din bits as follows. EQU D.sub.i =1 if Vres.sub.i -1+Vco.sub.i &gt;0, and EQU D.sub.i =-1if Vres.sub.i -1+Vco.sub.i &lt;0 (6)
Gain variances are created by capacitor mismatch and by finite operational amplifier gain and settling. Any of the above errors which affect the gain, such as those depicted in FIGS. 6B and 6C, will cause differential nonlinearity problems with the converter. If the cascade of N converters has a gain larger than 2.sup.N and the overall error is more than 1 least significant bit, then at least one A/D converter output code will correspond to a range of input voltages greater than the minimum required resolution of the converter. On the other hand, if the gain of the cascade is less than 2.sup.N by at least one least significant bit, then missing output codes will result since some output codes will be skipped as the input changes incrementally.
Moreover, if the output residue of a stage happens to be above +V.sub.ref or below -V.sub.ref for any reason, then the output bits of remaining subsequent stages will all latch to +1 or -1 respectively. This can occur as a consequence of any of the previously mentioned sources of error, such as too large a gain or vertical or horizontal shifting, if the input voltage just happens to place the output of that stage outside the acceptable range. The phenomenon occurs because an output above +V.sub.ref or below -V.sub.ref necessarily supplies the next stage with an input which is outside its intended range. That stage will supply the following stage with an output which is twice is far out of range as its input was. Essentially, once the output one stage goes out of range, that excess is multiplied by the gain factor for each additional stage. After very few stages, all the remaining stages are outputting residues that are essentially either the positive or negative supply voltage, and all the remaining coded bits coming out after that stage reaches the power supply limitation are meaningless.
The typical way that has been used to protect against this very catastrophic situation is to introduce an intentionally reduced gain. (Radix 1.95 is typical.) FIG. 7 shows the transfer function of a Radix&lt;2 stage. The range of possible outputs is less than -V.sub.ref to +V.sub.ref. This allows for a margin of error which can be designed large enough so that it is extremely unlikely that any of the errors will put the output voltage outside the acceptable input range. If any of the above-mentioned errors significantly affect the shape of the transfer curve, they can be accommodated by the built-in safety zone.
Unfortunately, however, the reduced gain necessitates the use of more stages to encode the overall output. Since the output bits now are essentially base 1.95 rather than base 2 numbers, and a complex correction equivalent to a series of nested multiplications is required to do the final conversion.
The major drawback with all of the systems using radix less than two techniques is that they require this large complex conversion circuit to transform the number from a radix less than 2 representation into a true binary base 2 representation. In many systems, this final translation is so complex that it is performed in software, greatly adding to the latency of the corrected output. If the final translation is implemented in hardware, and especially if that hardware is designed to run at frequencies as high as 40 MHz, this final conversion uses an inordinately large amount of power, silicon area, and generates noise which interferes with the performance of the analog sections of the A/D converter system. The proposed architecture of the present invention eliminates the need for a radix conversion circuit.
A second pipelined converter evolutionary path has developed independently which utilizes large amount of redundancy. The technique has been referred to as a "1.5 bit per stage pipelined" architecture. The 1.5 bit stage derives its name from the fact that each stage has three possible outputs, rather than only two in 1 bit stages. This amount of redundancy, which asymptotically approaches 100% as the number of output bits N increases, eliminates the effects of comparator offset errors up to V.sub.ref /4. This technique appears to be manufacturable up to the 10-bit level, at 20 MS/sec. For accuracies greater than 10-bits, calibration becomes necessary to compensate for the other errors due to capacitor mismatch, operational amplifier offset, charge injection, and finite operational amplifier gain and settling.
The 1.5 bit per stage architectures derive their insensitivity to analog to digital subconverter offsets by reducing their gain by a factor of two. The most typical configurations detect two bits per stage but with an interstage gain of two instead of four. Then it was realized that the two bits per stage could be achieved with only two comparators per stage, thereby reducing power. See S. Lewis, et al., "A 10-bit 20 Msample/s Analog-Digital-Converter", IEEE J. Solid State Circuits, vol. SC-27, no.3, pp. 351-358, March 1992. The two comparators per stage only realize three states instead of four, but the fourth state can be inferred by carry overflow in the final arithmetic. Because there are three states, requiring two bits, detected per stage but the interstage gain is two, a redundancy level of almost 100% is realized. A N-stage A/D converter, with no nonlinearities, has 2.sup.N+1 output codes but has 2(2.sup.(N+1) -N-2) unique states. Some of the unique states represent the same output codes. Thus, two or more unique states may represent the same output code. So an 11 stage converter ideally has 4096 output codes but 8166 states. In other words, 4070 states are redundant in that they represent the same output codes which are already represented by some other state.
The residue of the 1.5 bit per stage converter is shown in FIG. 8. In the middle portion of the transfer function the ideal peaks at the transitions are only +V.sub.ref /2 and -V.sub.ref /2. This residue design solves the problem of errors due to charge injection and offset in that there is room for .+-.V.sub.ref /2 error due to incorrect decision levels or charge injection. The equation of the transfer characteristic is the same as that for the one bit per stage design--Equation 3. However, the equation for the data bits detected at each stage is different. EQU D.sub.i =1 if V.sub.res &gt;+V.sub.ref /4, EQU D.sub.i =0 if -V.sub.ref /4&lt;V.sub.res &lt;+V.sub.ref /4, and EQU D.sub.i =-1 if V.sub.res &lt;-V.sub.ref /4. (7)
The digitized representation of the input voltage is as follows. ##EQU1##
At this point it is useful to consider a numerical example. Consider a converter with N=7; this produces an 8 bit output code. The output sequence in Table 1 was generated thorough simulation given an increasing analog input voltage with large random gain errors on the order of 5 %.
The first noteworthy observation is that several of the codes are represented by more than one set of output bit sequences. For instance, 29, 30, 31, 32, and 33, are each non-uniquely represented in Table 1. For each of these redundancies, one of the following two relations holds true. EQU 2*D.sub.i +D.sub.i+1 =-1 (9A) EQU 2*D.sub.i +D.sub.i+1 =1 (9B)
What this means, for example, is that 3 can be represented as 1(4)+-1(2)+1(1) or as 1(4)+0(2)+-1(1). In this example D.sub.i is the second least significant bit, and D.sub.i is the least significant bit, such that 2*D.sub.i +D.sub.i+1 =-1 since 2*-1+1 and 2*0+-1 both equal -1. To illustrate the other situation, 5 can be represented as 1(4)+0(2)+1(1) or as 1(4)+1(2)+-1(1). Here, D.sub.i is the second least significant bit, and D.sub.i+1 is the least significant bit, such that 2*D.sub.i +D.sub.i+1 =1 since 2*0+1 and 2*1+-1 both equal +1.
The second noteworthy observation is that the output codes are non-monotonic. Since the analog input voltage increased steadily throughout the table, a proper A/D coding would have produced a monotonic output. This means that the output code should either increase or remain the same at each subsequent sample, but it should never decrease. Here, the output code jumps from 32 back to 30 in the middle of the table. This is a perfect example of a non-monotonic output.
FIGS. 9A, 9B, and 9C show an analog input and two A/D converted output codes as an illustration of the difference between monotonic and non-monotonic outputs. FIG. 9A shows the analog input; FIG. 9B shows a non-monotonic output; FIG. 9C shows a monotonic output.
The 1.5 bit per stage structure is extremely insensitive to offsets due to the operational amplifier, charge injection, and the A/D subconverter comparator. However, it does not correct for linearity errors due to finite operational amplifier gain and/or capacitor mismatch.
Several implementations exist that provide a "self-calibration" scheme. See S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, And T. R. Viswanathan, "A 10-bit 20 Msample/s Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. SC-27, pp. 351-358, March 1992; B. Ginetti P. G. A. Jespers, and A. Vandemeulebroecke, "A CMOS 13-b Cyclic RSD A/D Converter," IEEE J. Solid-State Circuits, vol. SC-27, pp. 957-965, July 1992; H. S. Lee, "A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC," IEEE J. Solid-State Circuits, vol. SC-29, pp. 509-515, April 1994. None of these schemes can guarantee a monotonic characteristic after correction. Self-calibration uses the converter, in a calibration configuration, to measure the capacitor mismatch, and then forms a digital correction value based on the raw code. The monotonicity problem occurs for the very large class of A/D converter architectures in which multiple representations of the same output codes occur.
To illustrate the idea, a n-stage (n+1 bits) A/D converter with a 1.5 bit per stage implementation is considered. Each data bit D.sub.i can take three different values: 31 1, 0, +1. The digital representation of the input is given by the following equation. ##EQU2##
The self-calibrating correction algorithm adds a correction term to this digital representation. Very generally, this correction term is of the form below. ##EQU3##
In Equation 11, .phi..sub.i (.alpha..sub.0,.alpha..sub.1, . . . .alpha..sub.i) is a function of the capacitor mismatches for stage i and all preceding stages. If .alpha..sub.i represents the capacitor mismatches, the functions .phi..sub.i (.alpha..sub.0,.alpha..sub.1, . . . .alpha..sub.i) are given below. EQU .phi..sub.i *(.alpha..sub.0,.alpha..sub.1, . . . .alpha..sub.i)=2.sup.-(i+2)*(.alpha..sub.0 +.alpha..sub.1 +.alpha..sub.i-1 -.alpha..sub.i) (12)
In the ideal case when there are no gain errors, the total number of states in the converter can be calculated as 2.sup.n+2 -2*(n+2). As n gets larger, the average number of representations for each output code approaches two asymptotically. These multiple internal states occur at the common transition points of data bits D.sub.i and D.sub.i+1 with the rest of the data bits unchanged. From residue considerations, the following multiple representations appear in sequence for increasing input values. EQU D.sub.i 32 -1, D.sub.i+1 =1 (13a) EQU D.sub.i =0, D.sub.i+1 =-1 (13b)
Equations 13a and 13b are the solutions to Equation 9A. If all other raw output data bits are the same, and if one output satisfies Equation 13a while the other satisfies Equation 13b, both outputs represent the same code and thus are dual representations of the same code. However, the analog input that generated the raw output corresponding to Equation 13a was lower than the other by an amount less than 1 least significant bit of precision. Similarly, the following equations are the solutions to Equation 9b. EQU D.sub.i =0, D.sub.i+1 =1 (14a) EQU D.sub.i =1, D.sub.i+1 =-1 (14b)
It is also true that the analog input that produced the raw output corresponding to Equation 14a was lower than the other by an amount less than 1 least significant bit of precision.
Therefore, a necessary condition for monotonicity is that whenever multiple representations of the form 13a and 13b occur, the correction term (Equation 11) calculated for the representation 13a is less than the corresponding correction term for 13b. The same must be valid for multiple representations of the forms 14a and 14b.
For any stage that has only two non-zero output values which are negatives of each other, such as a 1.5 bit per stage converter or a 1-bit per stage converter, a linear correction algorithm is one that assumes that the correction value for the positive output is the negative of the correction value for the negative output.
Using any linear correction algorithm, the necessary conditions for monotonicity become the following.
for all i=0,1, . . . n-2, EQU .phi.(.alpha..sub.0, .alpha..sub.1, . . . .alpha..sub.i).gtoreq.2.phi..sub.i+1 *(.alpha..sub.0, .alpha..sub.1, . . . .alpha..sub.i+1) (15)
Substituting the relations of Equation 9, into the constraints in Equations 12, the monotonicity conditions are as follows. EQU .alpha..sub.i+1 .gtoreq.2*.alpha..sub.i, for i=0,1, . . . n-2(16)
The constraints in 16 are equivalent to a reduced nominal gain for each calibrated stage. Equation 16 established restrictions on the gain mismatches, which are not apriori satisfied. This further implies that non-monotonic behavior may occur even after the digital correction, or, equivalently, the correction algorithm can not guarantee the converter's monotonicity.
In the example shown in Table 1, the non-monotonic behavior of the raw output code is generated by the interstage gain errors. The correction algorithm should be able to identify all possible multiple representations and correctly resolve the monotonicity conditions. However, since the gain mismatches are essentially random, it is impossible to guarantee the satisfaction of the constraints in 16.
The powerful conclusion that can be dram from Equation 15 is that monotonicity can not be guaranteed in general for arbitrary gain mismatches for any A/D converter architecture that generates multiple representations of the same output code. This conclusion is valid for any linear correction algorithm that computes an error term as a function of stored self-calibrating data and raw data bits.